The present invention relates to a deflectional system for a television set comprising a power transistor and a driving circuit means and more, particularly to a driving circuit which supplies a deflecting current, increasing in a ramp-shaped manner, to a deflection coil, the driving circuit being periodically fed with switching-on pulses of a duration corresponding to the ramp length of the deflecting current, and applying an increasing switched-on base current to the power transistor during the switching-on pulse duration, the switched-on base current driving the power transistor into the saturation state during substantially the entire switching-on pulse duration, and after termination of the switching-on pulse, the driving circuit controlling the power transistor with a switching-off base current which rapidly decreases in relation to the increase of the switched-on base current and finally changes polarity and which effects a rapid return of the power transistor from the saturation state into the blocking state.
This deflectional system is intended to be used mainly in the horizontal deflection stage of television sets and video monitors. Conventional circuits for driving the power transistor in the horizontal deflection stage are realized by discrete component parts. Three characteristic examples of such conventional circuits are shown in FIGS. 1A, 1B and 1C. All three of these circuits comprise a power transistor LT the collector of which supplies current to a deflection coil L and the base circuit of which is connected to a driver circuit via a transformer T. Each driver circuit comprises a control transistor ST to the base of which line-frequency switching-on pulses can be supplied, which bring the control transistor ST into the conducting state.
On the collector side of the power transistor LT, there is provided a complex circuit which, when the voltage across the deflection coil L is constant, effects a current increasing with a constant steepness, as long as the power transistor LT is switched into the conductive state and is capable of supplying a correspondingly high current. In order to be able to maintain the condition of a constant voltage across the deflection coil L, one takes care that the emitter-collector path of the power transistor LT has a constant voltage drop during the switching-on time. This is achieved by driving the power transistor LT into the saturation state during its switching-on time. For doing so, it is necessary to have a minimum base current supplied to the power transistor at all times of the switching-on duration of the switching-on pulse.
FIGS. 2A and 2B show the collector current IC which increases in ramp-shaped manner and, respectively, the path of the base current IB1 with which the power transistor is driven. The two current curves are determined by the constant passive components of the circuit network surrounding the power transistor.
Due to the fact that the power transistor is driven into the saturation state during its switching-on duration, the power transistor can be switched-off only with a switching-off delay within which the base of the saturated transistor is discharged. Thus, the ramp-shaped increase of the collector current IC does not last only from the switching-on moment tE to the switching-off moment tA of the switching-on pulse supplied to the control transistor ST; the collector current IC returns to zero only after expiration of a storage time tS which effects the switching-off delay. The length of the storage time depends on the steepness of the switching-off base current in the period between the moments tA and tS. Due to the fact that during this switching-off operation, the collector current and the collector voltage of the power transistor simultaneously have finite values, it is possible that considerable power dissipation occurs during this switching-off operation, which may be in the range of up to several hundred watts and which is determinative for the power dissipation in the power transistor to a special degree. In order to reduce the period of time during which such high power dissipation occurs and, furthermore, in order to have the power transistor in due time ready for the next deflection interval, one makes the descending slope of the switching-off base current to be as steep as possible. However, there is a limit to doing so, due to the fact that in case of a too steep descending slope of the switching-off base current an inhomogenuous base discharge is caused which leads to the so-called "emitter crowding" effect, which is an undesired effect. If one makes the descending slope to be too shallow the high power dissipation can occur for too long a period of time and can cause damage to the power transistor. Between these two extremes there is an optimum descending slope which is determined by the dimensioning of the network surrounding the power transistor.
The current gain of the power transistor is a non-linear function of the collector current, with the current gain decreasing to a relatively strong extent when the collector current values become greater. Due to the fact that the path of the base current IB1, which is determined by the circuit network, displays a curve with a monotonously decreasing ascending slope in the switching-on period between tE and tA, the degree of saturation of the power transistor is smaller when the collector current IC at the switching-off moment tA has a larger value, and the degree of saturation is greater when the collector current at the switching-off moment has a smaller value. Due to the fact that the descending slope of the base current is determined by the network surrounding the power transistor, a shorter storage time results in case of greater final values of the collector current and a longer storage time results in case of smaller final values of the collector current.
The horizontal deflection stage has a (not shown) signal processing circuit associated therewith, which determines the deflection frequency and the image position, i.e. the phase position of the deflection signal. This circuit includes a control loop which is usually designated as 2 controller and controls the phase position between the line flyback signal and the horizontal generator. The line flyback signal is created when the power transistor becomes highly resistive, i.e. when the collector current IC returns to zero at the end of the storage time tS. In adaptation to the behavior of the network surrounding the power transistor, this control loop is designed such that it effects a discharging time or storage time which is inversely proportional to the final value of the collector current.
The known driving circuits the most typical examples of which are shown in FIGS. 1A, 1B and 1C, are each designed for a specific deflection frequency and for a specific final deflecting current. If a higher deflection frequency is required, e.g. for a video monitor with a higher resolution, or if different final values of the deflecting current and thus of the collector current IC are required, e.g. for different screen sizes and/or for picture tubes with differing maximum deflection angles, the known driving circuits must be designed in a different manner. This means that a correspondingly large number of driving circuits must be made available for the numerous different types of television sets and monitors and that the driving circuits must be given a new design in case of changed requirements.